A semiconductor memory device which can electrically erase information written in the memory cells is proposed.
In such semiconductor memory device, an erasure verification for judging whether or not information stored in a memory cell has been erased is performed.
The erasure verification is performed, e.g., by comparing a current flowing in a memory cell with a current flowing in a reference memory cell for an erasure verification by using a differential sense amplifier or others.
Related references are as follows:
Japanese Laid-open Patent Publication No. 2010-55679;
Japanese Laid-open Patent Publication No. 2001-243783; and
Japanese Laid-open Patent Publication No. 2010-176832.